PROJECT-BASED LEARNING IN COMPUTER ARCHITECTURE EDUCATION: DEVELOPMENT OF A RISC-V PROCESSOR IN VERILOG

Abstract

This article presents the implementation of a processor based on the fifth-generation Reduced Instruction Set Computer architecture (RISC-V32I), described in Verilog HDL 2001. The study aimed to develop a Project-Based Learning (PBL) approach that connects concepts in computer architecture and digital circuits with practical hardware development. The methodology followed a 17-week schedule involving theoretical preparation, incremental implementation of a five-stage pipeline, functional validation through simulation, and evaluation of the students' learning experience. ModelSim and Intel Quartus Prime were used for simulation, synthesis, and project debugging. The results demonstrated the implementation of the processor datapath, functional validation of instruction execution, and the development of a text-based interface for pipeline monitoring. The findings indicate that the proposed approach contributed to consolidating technical and cognitive skills by connecting theoretical concepts with practical hardware development activities. Finally, an assessment of the students' perception of the learning experience was conducted, considering the competencies mobilized during the project and the cognitive levels of Bloom's Taxonomy.